The pace of microelectronics development at the chip level has out-stripped the capacity of the package to match the chip performance and carry it through to the system level. A simple example can make the point. Assume that over a period of time we can fabricate devices of half the area previously achievable, in chips of twice the previous size, giving four times the number of circuits per device, four times the power dissipation, and about twice as many leads required. For the same peripheral-lead package size, the leads must be closer together and thinner, producing increased inductance and crosstalk and a greater probability of fatigue failure, exacerbated by the higher power dissipation, which also creates higher mechanical stress in the package. And in a CMOS digital system, if one also takes advantage of the clock frequency increase possible with smaller devices, these problems increase even more. The example demonstrates that the semiconductor device package has become the bottleneck to the transfer of silicon capabilities to system performances. The obvious consequence of this development is the economic significance of packaging technologies to microelectronics industries (e.g. Intel, ON Semiconductor, Motorola). Obviously the increasing importance of component packaging to industry also drives a growing need for engineering graduates with experience in the field. And the IEEE Transactions on Advanced Packaging reports developments for those engineers active in packaging development.
Electrical engineers in the packaging field are often primarily concerned with the electrical effects of shrinking device sizes and faster operation, i.e. pulse reflections on the “transmission line” interconnections, crosstalk, stray inductance, switching noise, electromagnetic compatibility (EMC), etc. These effects are the reason why the microelectronics industry is moving to lower power supply voltages, reducing noise margins which are already threatened by the increased noise levels. But notice that the traditional academic fields represented in the example above include electrical, mechanical, thermal, and materials engineering, to which one can add reliability, chemistry, applied physics, and math. The true “packaging engineer” needs a more multi-disciplinary background than is conventionally found in a single undergraduate major, and well-prepared graduates are therefore hard to find and are in demand. Electronics Packaging courses are only now starting to be found at the senior elective level, instead of just in graduate programs, and clearly more BS graduates will find jobs in this increasingly important field in the future. The best preparation for an EE student would be dual concentrations in Microelectronics (Materials & Devices) and Electromagnetism (Guided Waves), supplemented by a solid sophomore base (or more advanced) in Materials, Statics (Strength of Materials), Heat Transfer, etc. Packaging graduates also find jobs in Aerospace companies (e.g. Lockheed Martin), in the Computer field (e.g. Sun Microsystems), in Communications (e.g. Nokia or Ericsson), in the more recent optoelectronics device area (e.g. Lucent Technologies), etc.
